The present invention generally relates to semiconductor processing, and in particular to a method for producing small space patterns via employment of a plasma polymerization layer.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photo mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The spacing between adjacent lines of an integrated circuit is an important dimension, and ever continuing efforts are made toward reducing such spacing dimension. The wavelength of light used in the photolithographic process along with the lithographic tool set employed in the process generally dictate the spacing dimension. For example, a tool set designed to provide lines and/or spaces at 0.18 xcexcm does not achieve consistent lines and/or spacing at its minimum range of 0.18 xcexcm but rather is employed to generate lines and/or spacing above the minimum range (e.g., 0.20 xcexcm) with fairly consistent results.
In view of the above, it would be desirable for a technique which allows for a particular lithographic tool set to be employed and achieve consistent lines and/or spacing between lines at the minimum range of the tool set and even below the minimum range.
The present invention relates to a method for employing a photolithographic tool set and achieving substantially consistent spacing dimensions below the minimum range of the tool set. A given photolithographic tool set is employed to pattern a photoresist layer in a desired fashion. The tool set is capable of achieving a smallest spacing dimension between adjacent lines of d1. After the photoresist layer is patterned, a plasma polymerization layer is conformably deposited over the patterned photoresist layer. Thereafter, a directional etch is performed to remove a particular amount of the polymerization layer (preferably a thickness equivalent to the thickness of the polymerization layer residing over a photoresist portion). The directional etch leaves polymer sidewalls along the patterned photoresist portions which result in a reduction in dimension size of exposed areas interposed between adjacent photoresist portions. Thus a spacing dimension size (d2) of exposed areas is substantially less than the spacing dimension size (d1) of exposed areas prior to the depositing the polymerization layer. An etch step is performed to etch layers underlying the photoresist. Adjacent lines etched from one of the underlayers will have a smallest spacing design dimension of d2 as compared to d1. Thus, the present invention provides for achieving spacing dimensions between lines at and below a minimum patterning range for a particular lithographic tool set.
One aspect of the invention relates to a method for forming an etch mask. A photoresist layer is patterned, wherein d1 is a smallest space dimension of an exposed area of a layer underlying the photoresist layer. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of the underlayer. The polymer layer is etched to form polymer sidewalls, the polymer sidewalls reducing the smallest space dimension of the exposed underlayer area to d2, wherein d2 less than d1.
Another aspect of the invention relates to a method for producing a small space pattern in a semiconductor layer. A photoresist layer of a semiconductor structure is patterned with a photolithographic tool set, a minimum printed space dimension of the patterned photoresist being d1, wherein d1 is the smallest space dimension consistently printable by the photolithographic tool set. A polymer layer is formed to be conformal to the patterned photoresist layer and exposed portions of a first layer underlying the photoresist layer, d1 being the smallest dimension of the exposed portions. The polymer layer is etched an amount substantially equivalent to a minimum thickness parameter (xcex3) of the polymer to leave polymer sidewalls such that the smallest dimension of the exposed portions is now d2, wherein d2 less than d1.
Another aspect of the invention relates to method of forming closely spaced lines from a polysilicon layer. A semiconductor structure is used, the semiconductor structure including: the polysilicon layer; an anti-reflective coating (ARC) layer over the polysilicon layer; and a patterned photoresist layer over the ARC layer, wherein a smallest dimension of at least one exposed portion of the ARC layer equals d1. A polymer layer is formed to conform to an exposed surface of the semiconductor structure. The polymer layer is etched so as to leave polymer portions along sidewalls of the photoresist layer, the polymer portions reducing the smallest dimension of the at least one exposed portion of the ARC layer to d2, wherein d2 less than d1.
Still another aspect of the invention relates to a method of forming closely spaced lines from a polysilicon layer. A photolithographic tool set is used to pattern a photoresist layer of a semiconductor structure wherein d1 is a smallest space dimension consistently printable by the photolithographic tool set, the semiconductor structure including: the polysilicon layer; an anti-reflective coating (ARC) layer over the polysilicon layer; and the patterned photoresist layer over the ARC layer, wherein a smallest dimension of at least one exposed portion of the ARC layer equals d1. The ARC layer is etched. The photoresist layer is removed. A polymer layer is formed to conform to remaining portions of the ARC layer and exposed portions of a polysilicon layer underlying the ARC layer. The polymer layer is etched so as to leave polymer sidewalls, the polymer sidewalls reducing the smallest dimension of the at least one exposed portion of the polysilicon layer to d2, wherein d2 less than d1. The polysilicon layer is etched, wherein a smallest space dimension between at least two adjacent lines is substantially equal to d2.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.